Semiconductor high-speed integrated electro-optic devices and methods

ABSTRACT

Novel integrated electro-optic structures such as modulators and switches and methods for fabrication of the same are disclosed in a variety of embodiments. In an illustrative embodiment, a device includes a substrate with a waveguide and an optical resonator comprising polycrystalline silicon positioned on the substrate. First and second doped semiconducting regions also comprise polycrystalline silicon and are positioned proximate to the first optical resonator. The first optical resonator is communicatively coupled to the waveguide.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to the prior-filed provisional patent application with Ser. No. 61/314,466, entitled “Silicon high-speed integrated electro-optic devices and methods”, filed Mar. 16, 2010, the entirety of which is incorporated by reference herein.

STATEMENT REGARDING FEDERALLY FUNDED RESEARCH OR DEVELOPMENT

This invention was made with U.S. government support under grant number ECS-0335765 awarded by the United States National Science Foundation (NSF). The United States Government has certain rights in the invention.

FIELD

The invention relates to electro-optic devices in general and more particularly to deposited semiconductor electro-optical devices.

BACKGROUND

Photonic networks on a silicon microelectronic chip offer the opportunity to overcome the power and bandwidth limitations in traditional microprocessor interconnects. One device for on-chip optical networks is a high-speed silicon electro-optic modulator.

All previous examples of silicon micrometer-scale modulators have been fabricated on single-crystalline silicon-on-insulator (SOI) wafers. The basic device structure is an optical resonator embedded in a diode. The diode is used to inject and extract charge from the resonator, which switches the light transmission on and off using the free carrier plasma dispersion effect.

Reliance on the SOI platform presents two difficult challenges for the integration of optics with microprocessor ships. First, crystalline SOI is the same material that electrical transistors are made from, and the large-scale integration of hundreds of optical devices required for an optical network would take a prohibitive amount of real estate away from transistors in the same silicon layer. Second, the buried oxide thickness in standard microelectronic SOI is much smaller than the optical wavelength and, therefore, not appropriate for a waveguide cladding.

The discussion above is merely provided for general background information and is not intended to be used as an aid in determining the scope of the claimed subject matter.

SUMMARY

Novel integrated high-speed electro-optic structures and methods for fabrication of the same are disclosed in a variety of embodiments. In an illustrative embodiment, a device includes a substrate, a first waveguide comprising polycrystalline silicon positioned on the substrate, and a first optical resonator comprising polycrystalline silicon positioned on the substrate. First and second doped semiconducting regions comprising polycrystalline silicon are positioned proximate to the first optical resonator. The first optical resonator is communicatively coupled to the first waveguide.

In another illustrative embodiment, a method includes providing an insulating base layer; forming an amorphous semiconductor layer on the base layer; and modifying at least a portion of the amorphous semiconductor layer into a polycrystalline semiconductor layer. The method further includes background doping a target area of the polycrystalline semiconductor layer; forming a waveguide and a resonator in the polycrystalline semiconductor layer, comprising at least one step of lithography and/or etching, wherein the resonator is formed in the background doped target area; forming a p-type region in the polycrystalline semiconductor layer proximate to the resonator, comprising at least one step of applying a p-type dopant; and forming an n-type region in the polycrystalline semiconductor layer proximate to the resonator, comprising at least one step of applying an n-type dopant.

This Summary is intended only to provide a brief overview of subject matter disclosed herein according to one or more illustrative embodiments, and does not serve as a guide to interpreting the claims or to define or limit the scope of the invention, which is defined only by the appended claims. This Summary is provided to introduce an illustrative selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the background.

BRIEF DESCRIPTION OF THE DRAWINGS

For a further understanding of the objects of the various illustrative embodiments, reference will be made to the following detailed description which is to be read in connection with the accompanying drawings.

FIG. 1 a depicts a top plan schematic view of an electro-optic modulator, in accordance with an illustrative embodiment.

FIG. 1 b depicts a perspective view based on a scanning electron microscope (SEM) image of an electro-optic modulator, in accordance with an illustrative embodiment.

FIG. 1 c depicts a cross-section side plan schematic view of a section of an electro-optic modulator, in accordance with an illustrative embodiment.

FIG. 1 d depicts a top plan schematic view of a multiple-resonator electro-optic modulator, in accordance with an illustrative embodiment.

FIG. 2 a depicts a graph of optical transmission per wavelength through an electro-optic modulator in accordance with an illustrative embodiment.

FIG. 2 b depicts a graph of current per bias voltage through an electro-optic modulator in accordance with an illustrative embodiment.

FIG. 3 a depicts a graph of experimentally measured optical signal transmission through an electro-optic modulator in response to a voltage signal in accordance with an illustrative embodiment.

FIG. 3 b depicts a graph of a frame-averaged optical eye diagram for an experimentally measured optical signal transmission through an electro-optic modulator in response to a voltage signal in accordance with an illustrative embodiment.

FIG. 3 c depicts a graph of simulated optical transmission through an electro-optic modulator in response to a voltage signal in accordance with an illustrative embodiment.

FIG. 4 depicts a series of fabrication steps for a method for fabricating an electro-optic device, in accordance with an illustrative embodiment.

FIG. 5 depicts a top plan schematic view of an electro-optic switch, in accordance with an illustrative embodiment.

The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of various embodiments. In the drawings, like numerals are used to indicate like parts throughout the various views.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Set forth herein are novel integrated electro-optic devices such as electro-optic modulators and novel methods for fabricating integrated electro-optic structures, in accordance with a variety of embodiments. FIG. 1 a depicts a top plan schematic view of an electro-optic modulator 101, as an example of one type of electro-optic device of the present disclosure. Electro-optic modulator 101 includes a substrate 100 that may be formed of a deposited microelectronic material, such as polycrystalline silicon (i.e. polysilicon), for example. In other implementations, substrate 100 may be formed from at least one of another form of silicon, germanium, or a compound semiconductor such as gallium arsenide or indium phosphide, for example. Electro-optic modulator 101 further includes a first optical resonator 103, a p-type doped semiconducting region 105, n-type doped semiconducting regions 107 and 109, and a first waveguide 111, positioned on the substrate 100. The optical resonator 103 is positioned relative to the waveguide 111 such as to enable optical coupling between the optical resonator 103 and the waveguide 111. Optical resonator 103 is thereby communicatively coupled to the waveguide 111, so that electrical signals provided to at least one of the doped semiconducting regions 105, 107, 109 can control the resonant wavelength of optical resonator 103, and thereby control the transmission of an optical signal, depicted here as input signal 115 and output signal 117, along waveguide 111.

First optical resonator 103 is a ring resonator in this example. Other optical resonators such as a microdisk or a photonic crystal may be used in various implementations. The p-type doped semiconducting region 105 and the n-type doped semiconducting regions 107, 109 are positioned proximate to the optical resonator 103, in this example. In particular, the p-type doped semiconducting region 105 is positioned interior to the optical resonator 103, and the n-type doped semiconducting regions 107, 109 and the waveguide 111 are positioned exterior to the optical resonator 103, in this example. The p-type doped semiconducting region 105 and the n-type doped semiconducting regions 107, 109 are positioned proximate to the first optical resonator 103 to function as p⁺ and n⁺ regions of a p⁺n⁻n⁺ diode with optical resonator 103.

Waveguide 111 may be configured for transmission of optical signals, and may be formed with dimensions optimized for transmission on a particular wavelength or spectrum of wavelengths depending on materials, operating conditions, and other relevant factors. In various examples, waveguide 111 may be suited for transmission of ultraviolet, visible or infrared wavelengths, and waveguide 111 may have a cross-sectional dimension within a range of 100 to 2,000 nanometers, for example.

Other physical arrangements and layouts of the various components may be used in other implementations, such as an n-type doped semiconducting region interior to a ring resonator and a p-type doped semiconducting region exterior to a ring resonator, or layouts that extend into multiple vertical layers, for example. The optical resonator 103 is communicatively coupled to the waveguide 111, in the example of FIG. 1 a. That is, optical resonator 103 is optically coupled to the waveguide 111, to allow signal communication between optical resonator 103 and waveguide 111. Waveguide 111 may be formed at least mostly from polycrystalline silicon, or another material such as silicon nitride or hydrogenated amorphous silicon, for example. Using these materials for forming the waveguides may assist in integrating an electro-optic device layer on top of another semiconductor layer such as a CMOS metal interconnect layer, and support feasibly integrating electro-optic functionality with other semiconductor and microelectronic fabrication, for example.

The p-type doped semiconducting region 105 may be considered to be a first doped semiconducting region, and the n-type doped semiconducting regions 107 and 109 may be considered to be second doped semiconducting regions, such that in other embodiments, one or more first doped semiconducting regions and one or more second doped semiconducting regions may be positioned proximate to the first optical resonator 103 in any functional arrangement. The first optical resonator 103 may also be doped with a background doping, which is an n-type background doping in this example but may be a p-type background doping in other embodiments. The p-type doped semiconducting region 105, the first optical resonator 103, and the n-type doped semiconducting regions 107 and 109 thereby form a p⁺n⁻n⁺ diode.

In an illustrative example, the substrate 100 may be formed of polycrystalline silicon, and various features may be formed from the same layer of polycrystalline silicon, using various techniques of deposition, etching, doping, annealing, and so forth. In this example, in electro-optic modulator 101, waveguide 111 may be formed from or include polycrystalline silicon, the first optical resonator 103 may be formed from or include polycrystalline silicon background doped with a background donor dopant, the p-type doped semiconducting region may be formed from or include polycrystalline silicon doped with an acceptor dopant, and the n-type doped semiconducting region may be formed from or include polycrystalline silicon doped with a donor dopant. The p-type and n-type doped semiconducting regions may be formed from or include polycrystalline silicon doped with acceptor and donor dopants, respectively, at a higher density than the background donor dopant in the first optical resonator 103.

For example, the background doping in the region of the first optical resonator 103 may have a concentration in a range of between 10¹¹ and 10¹⁸ charge carriers per square centimeter, and the p-type semiconducting region and the n-type semiconducting region may be doped with a concentration in a range of between 10¹⁴ and 10²² charge carriers per square centimeter, in various illustrative implementations. The p-type semiconducting region may include silicon doped with any type of acceptor dopant, such as one or more of boron, aluminum, or gallium, for example. The n-type semiconducting region may include silicon doped with any type of donor dopant, such as one or more of phosphorus, arsenic, or antimony, for example. The acceptor and donor dopants may be applied in an ionic form such as boron difluoride ion and phosphorus ion, for example. The acceptor and donor dopants may be applied using plasma enhanced chemical vapor deposition (PECVD), for example.

The electro-optic modulator 101 may be coated with an insulating cladding layer such as silicon dioxide, with electrical contacts made through the cladding to the diode elements such as p-type doped semiconducting region 105 and n-type doped semiconducting regions 107, 109, in an illustrative embodiment. FIG. 1 b depicts a perspective view based on a scanning electron microscope (SEM) image of the electro-optic modulator 101, in accordance with an illustrative embodiment consistent with that of FIG. 1 a, with a cladding 110 covering the substrate 100 and various elements formed thereon, including first optical resonator 103, doped semiconducting regions 105, 107, and 109, and waveguide 111. FIG. 1B also shows first optical resonator 103 and waveguide 111 covered with cladding 110.

A first conductive contact, which includes via 135 and surface contact pad 136, is connected to the p-type doped semiconducting region 105. A second conductive contact, which includes via 137 and surface contact pad 138, is connected to the n-type doped semiconducting regions 107 and 109. Vias 135, 137 extend through the cladding 110 between the surface portions and the doped semiconducting regions 105, 107, and 109, as is shown in FIG. 1 c. FIG. 1 c depicts a cross-section side plan schematic view of a section of electro-optic modulator 101, as another view of the illustrative embodiment of FIGS. 1 a and 1 b. A via 135 extends through the cladding 110 from p-type doped semiconducting region 105 to a contact pad 136, and another via 137 extends through the cladding 110 from n-type doped semiconducting regions 107, 109 to a contact pad 138. Contact pads 136, 138 may connect with conductive leads 132, 134 respectively that extend away from electro-optic modulator 101, as shown in FIG. 1B, to be available for connection with a larger circuitry infrastructure. For example, a metal interconnect layer (not shown) may be connected to the conductive contacts including surface contact pads 136, 138.

The electro-optic modulator 101 may function as an electrically controlled modulator. The electro-optic modulator 101 may include a tuning mechanism based on any of an electrical charge carrier, thermal, magnetic, photoelectric or microfluidic effect, or at least one of the above. For example, an electrical signal, in terms of a controllable signal such as voltage or current, for example, may be applied to electro-optic modulator 101, such as through the conductive leads 132, 134, which may shift the index of refraction and therefore the resonant wavelength of optical resonator 103, and thereby control the transmission of an optical signal along waveguide 111. This enables electro-optic modulator 101 to function as a modulator to enable electrical signals applied through conductive leads 132, 134 to be translated to an optical signal along waveguide 111. This effect can also be used to calibrate a resonator to correct for variations or defects resulting from manufacturing processes, for example.

FIG. 1 d depicts a top plan schematic view of a multiple-resonator electro-optic modulator, in accordance with an illustrative embodiment in which an array 201 of four optical resonators 241, 251, 261, and 271, in the form of microring resonators, are optically coupled to a single waveguide 211. Representative optical resonator 241 includes an optical resonator 213 that is communicatively coupled to waveguide 211, and p-type doped semiconducting region 205 and n-type doped semiconducting regions 207 and 209 proximate to optical resonator 213 thereby forming a p⁺n⁻n⁺ diode with optical resonator 213. Each of the optical resonators 241, 251, 261, and 271 in the array may therefore function as an independent modulator on waveguide 211. The four optical resonators 241, 251, 261, and 271 have different radii, which enables each one to operate at a different frequency, and enables the array of resonators to engage in multiplexing data in multiple wavelengths with the waveguide 211. Input data signals 202 along waveguide 211 may include wavelength-multiplexed data, and may be modulated by representative optical resonators 241, 251, 261, 271, and any other communicatively coupled elements to perform logic operations on different wavelength signals that determine the output wavelength-multiplexed data signals 204. The differences in radii of the resonators is exaggerated in the view of FIG. 1 d. The four resonators as depicted are merely illustrative of what could be tens, hundreds, thousands, or any number of different resonators optically coupled to single waveguide 211. Multiple resonators may also be optically coupled to additional waveguides on a single opto-electronic substrate or chip, for example.

In an array such as array 201 shown in FIG. 1 d, each of the optical resonators may be positioned at a distance from the waveguide to enable optical coupling of each particular optical resonator, with its own radius, to the waveguide, taking into account the dimensions, materials, and other relevant factors that affect optical coupling. The optical resonators may also be positioned relative to each other to prevent optical coupling between adjacent resonators, with enough spacing between the adjacent resonators, dependent on other factors such as materials and shielding between the resonators and the operating wavelengths of the resonators. For example, each resonator may be positioned somewhere in a range of 100 to 1,000 nanometers from the waveguide, while adjacent resonators may be positioned at least a couple of thousand nanometers away from each other, taking into account the materials, resonant wavelengths, and other relevant factors in a particular implementation.

In another example, an array may have multiple optical resonators of the same radius, and the array may also include tuning mechanisms associated with some or all of the optical resonators that enable the optical resonators to be in communication with the waveguide at different times, thereby enabling time multiplexing in the waveguide. Other implementations may use other photonic structures for multiplexing data in wavelength or time or in other controllable signal variables such as phase or amplitude, for example. Still other implementations may enable a combination of different multiplexing techniques. For example, an opto-electronic chip may have a set of different arrays with several microring resonators at a first radius, several other microring resonators at a second radius, and so forth all coupled to a single waveguide and controlled to multiplex in both wavelength and time along the single waveguide, for example.

In another example, an optical resonator may be positioned vertically proximate to the waveguide on different deposited layers of the substrate from each other, such that they are deposited or formed in separate fabrication steps, as opposed to being positioned horizontally proximate to each other as depicted in FIGS. 1 a, 1 b, and 1 d. One or more optical resonators may be optically coupled to the waveguide across a separation defined between different vertically stacked layers, so that a resonator may be stacked above or below the waveguide. This may be combined with formation in the same layer with horizontal separation, so that different resonators may be positioned below, sideways from, and above a common waveguide, for example. Vertically stacked resonators and waveguides may also be formed to optimize the distance between the two for optical coupling, with positioning displacements generally in the range of 100 to 1,000 nanometers, depending on materials, wavelengths, and other relevant factors.

Vertical arrangements may also be repeated, so that there may be any number of multiple layers of stacked resonators and waveguides, combined with electrical connections such as electrical leads, vias, and interconnects, to provide the basis for a broad variety of three-dimensionally arranged, interconnected, and interacting electrical and optical elements in a single integrated electro-optic chip created with well-understood fabrication techniques for feasible scaling.

FIG. 4 depicts a flowchart for a method 400 according to an illustrative embodiment. Method 400 includes step 1, of providing an insulating base layer; step 2, of forming an amorphous semiconductor layer on the base layer; step 3, of modifying at least a portion of the amorphous semiconductor layer into a polycrystalline semiconductor layer; step 4, of background doping a target area of the polycrystalline semiconductor layer; step 5, of forming a waveguide and a resonator in the polycrystalline semiconductor layer, comprising at least one step of lithography and/or etching, wherein the resonator is formed in the background doped target area; step 6, of forming a p-type region in the polycrystalline semiconductor layer proximate to the resonator, comprising at least one step of applying a p-type dopant; and step 7, of forming an n-type region in the polycrystalline semiconductor layer proximate to the resonator, comprising at least one step of applying an n-type dopant. The order of these steps may be different, and other steps may also be used together with the steps listed here, in various embodiments.

Step 1 of providing an insulating base layer may involve providing a semiconductor substrate, such as forming a silicon dioxide layer or other type of oxide layer on a silicon wafer, as an illustrative example. This insulating layer may be hundreds of nanometers to one or more microns thick, and may be three microns thick in one illustrative example. Step 2, of forming an amorphous semiconductor layer on the base layer, may involve depositing amorphous silicon on the base layer, using low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), e-beam evaporation, sputtering, or some other deposition technique, for example. The amorphous semiconductor layer may be formed with a thickness within a range of 100 to 500 nanometers, or around one micron, or around three microns, or with other thicknesses smaller or greater than these ranges, in various implementations.

Step 3, of modifying at least a portion of the amorphous semiconductor layer into a polycrystalline semiconductor layer, may involve performing a thermal annealing of the amorphous silicon, thereby crystallizing part or all of the amorphous silicon into polycrystalline silicon, in an illustrative example. This annealing process may involve baking the wafer, such as at a maximum temperature of 1,100 degrees Celsius in an illustrative example. In another example, this annealing process may involve applying a laser with a wavelength of less than or equal to 400 nanometers and a pulse period of less than or equal to 200 nanoseconds to the amorphous semiconductor layer to crystallize it into a polycrystalline semiconductor layer. Such a process of laser annealing using sub-microsecond pulses may enable proper annealing of the layer of interest itself, i.e. the layer being crystallized in this step, without applying excessive heat to adjacent layers. This may be useful when this annealing step is part of fabricating a semiconductor electro-optic layer on top of one or more other electronic or electro-optic layers being formed in a multi-layer or otherwise three-dimensional chip. This is one example of enabling fabrication of at least one electro-optic layer adjacent to at least one electronic integrated circuit layer in a single fabrication process on a single wafer.

Step 4, of background doping a target area of the polycrystalline semiconductor layer, may involve opening windows in positive e-beam resist and performing ion implantation with a Group V dopant such as phosphorus, for example. In one illustrative example, phosphorus ions may be implanted with a dose of 4.7×10¹² cm⁻² or in a comparable range and with an energy of 130 keV or in a comparable range.

Step 5, of forming a waveguide and a resonator in the polycrystalline semiconductor layer, may include at least one step of lithography and/or etching, which may include e-beam lithography or photolithography and a resist such as XR-1541 resist, and transferring the pattern using an etching process such as chlorine-based inductively coupled plasma reactive ion etching (ICP-RIE). Other etchants may also be used such as hydrogen bromide (HBr), sulfur hexafluoride (SF₆), or octafluorocyclobutane (C₄F₈), for example. This may include forming the resonator in the background doped target area. Forming the resonator may also involve leaving or etching one or more slabs of silicon, with a thickness in the range of 40 nanometers, or within a range of 25 to 75 nanometers, for example, which may provide electrical access, and which may define an exterior of the resonator.

Step 6, of forming a p-type region in the polycrystalline semiconductor layer proximate to the resonator, may include at least one step of applying a p-type dopant such as boron, aluminum, or gallium, for example, and which may be done by ion implantation, for example. In one illustrative example, boron difluoride (BF₂) ion implantation may be performed in a dose in the range of 1.2*10¹⁵ cm⁻², for example. Step 7, of forming an n-type region in the polycrystalline semiconductor layer proximate to the resonator, may include at least one step of applying an n-type dopant such as phosphorus, arsenic, or antimony, for example, and which may be done by ion implantation, for example. In one illustrative example, phosphorus ion implantation may be performed, also in a dose in the range of 1.2*10¹⁵ cm⁻², for example.

Various embodiments of method 400 may also include one or more steps of annealing the polycrystalline semiconductor layer after forming the waveguide, the resonator, the p-type region, and the n-type region in the polycrystalline semiconductor layer. In some implementations, this step of annealing the polycrystalline semiconductor layer may involve baking the polycrystalline semiconductor layer for two or more periods at temperatures within a range of 600 to 1,050 degrees Celsius, for example. In other implementations, this step of annealing the polycrystalline semiconductor layer may involve short-period laser annealing, such as with an excimer or other high-frequency laser with pulse periods in the hundreds of nanoseconds, for example.

Various embodiments of method 400 may also include providing an insulating cladding on the polycrystalline semiconductor layer, forming vias in contact with the p-type region and the n-type region through the insulating cladding, and forming conductive contacts on surfaces of the vias, as described with reference to FIGS. 1 b and 1 c above, for example.

FIG. 5 depicts a top plan schematic view of an electro-optic switch 501, as another example of a type of electro-optic device of the present disclosure. Electro-optic switch 501 is analogous in some respects to electro-optic modulator 101 of FIG. 1 a, in that it includes an optical resonator 503 formed as part of a p⁺n⁻n⁺ diode, between p-type doped semiconducting region 505 and n-type doped semiconducting regions 507, 509, and 510. Optical resonator 503 is also communicatively coupled to a first waveguide 511, and also to a second waveguide 512. Electro-optic switch 501 can thereby allow input optical signals 513 on waveguide 511 to continue transmitting as output optical signals 515 along waveguide 511, or can translate optical input signals 513 on waveguide 511 into new optical signals 516 transmitting on waveguide 512.

In particular, electro-optic switch 501 can be controlled through electrical signals through contacts with one or more of the doped semiconducting regions 505, 507, 509, and 510 to adjust the internal index of refraction and therefore the resonant wavelength of optical resonator 503. In an off state of electro-optic switch 501, the resonant wavelength of optical resonator 503 is kept different from the wavelength of the input signals 513, which allows transmission of input signals 513 along the first waveguide 511 as output signals 515. Electro-optic switch 501 may also be set into an on state, in which the resonant wavelength of optical resonator 503 is tuned to the same wavelength of the input signals 513, which allows translation of input signals 513 from the first waveguide 511 to the second waveguide 512 as output signals 516.

Multiple electro-optic modulators and switches may be provided in any of a wide variety of arrangements, including multiple electro-optic modulators and/or switches optically coupled to any number of waveguides, and with modulators or switches optically coupled to waveguides laterally within the same electro-optic layer or vertically across adjacent electro-optic layers. For example, an electro-optic switch otherwise similar to electro-optic switch 501 of FIG. 5 may be optically coupled to one or more waveguides that are positioned above or below the electro-optic switch in a different electro-optic device layer, formed in a separate series of fabrication steps. Analogous switching mechanisms may also be used in other implementations that modulate or switch data in time, phase, or amplitude, for example.

Additional illustrative examples of devices and methods within the scope of this disclosure are provided below with reference to the corresponding provisional patent application. The devices and methods within the disclosure below are all illustrative examples and do not serve to limit the scope or exclude other implementations within the complete scope of the appended claims. FIGS. 1 a, 1 b, and 1 c are referenced below as FIGS. 1 . . . (a), (b), and (c); FIGS. 2 a and 2 b are referenced below as FIGS. 2 (a) and (b); and FIGS. 3 a, 3 b, and 3 c are referenced below as FIGS. 3 . . . (a) . . . (b) . . . and (c).

Appendix: Illustrative Examples from Provisional Application

There is set forth herein embodiments of methods and devices capable of GHz-speed electro-optic modulation (e.g., in a deposited microelectronic film). The use of deposited material, here polycrystalline silicon (polysilicon), would enable the monolithic integration of optics in a separate layer of a microprocessor chip and provide the flexibility needed for optical system design. Exemplary electro-optic functionality is demonstrated by embedding a p⁺n⁻n⁺ diode around a polysilicon ring resonator. In order to achieve good optical and electrical properties, we use photonic structures with cross-sectional dimensions of hundreds of nanometers, approximately the same dimensions as the material grain size. This can enable sub-nanosecond carrier injection and optical modulation using the free carrier dispersion effect.

According to one aspect of the application, there is provided an electro-optic device such as a high speed micrometer-scale electro-optic modulator based on the enhancement of silicon's free carrier dispersion effect by a ring resonant structure.

According to one aspect of the application, there is provided an electro-optic device such as modulator fabricated in a deposited thin film of polycrystalline silicon. The thin film can be deposited by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), e-beam evaporation, or sputtering, all of which are standard silicon CMOS fabrication techniques. The thin film can be deposited in either the amorphous phase or the polycrystalline phase. The thin film can be annealed to improve its optical and electrical properties by furnace thermal annealing, rapid thermal annealing, or excimer laser annealing. The thin film can be protected by a silicon dioxide or silicon nitride layer during an anneal. The thin film may be chemical-mechanical polished (CMP) after annealing to decrease top surface roughness.

According to one aspect of the application, there is provided an electro-optic device such as a modulator that can be either laterally coupled or vertically coupled to a bus waveguide. The bus waveguide can be fabricated from crystalline silicon, polycrystalline silicon, amorphous silicon, silicon nitride, or silicon oxynitride.

According to one aspect of the application, there is provided an electro-optic device such as a modulator that can be completely surrounded by the p-i-n diode, (e.g., using a vertical coupling scheme).

According to one aspect of the application, there is provided an electro-optic device such as a modulator that can be deposited and fabricated either in the front end of a CMOS process (e.g., below the metal interconnect layers) or in the back end of a CMOS process (e.g., above the metal interconnect layer) given that the CMOS temperature requirements are met.

According to one aspect of the application, embodiments are provided that can increase substantially the number of modulators that can fit on a chip by depositing multiple layers of polysilicon.

According to one aspect, there is provided an integrated circuit element for optical data transmission on a microprocessor chip incorporating embodiments of electro-optic devices and/or methods according to the application.

According to one aspect, embodiments according to the application can be used either as a stand alone modulator or as an integrated circuit element.

According to one aspect, embodiments according to the application can be used for exemplary data transmission rates of 10 Gbps or 40 Gbps when used in a 4-channel or 16-channel wavelength division multiplexing (WDM) scheme.

According to one aspect, embodiments according to the application can be used for intra-chip, chip-to-chip, rack-to-rack, and long haul data transmission as part of an electronic, photonic, or electro-optic chip.

Details of the above described embodiments and additional embodiments are set forth in the manuscript entitled, Deposited silicon high-speed integrated electro-optic modulator, which is attached hereto as Appendix A, Exemplary Fabrication Description, which is attached hereto as Appendix B, and additional references, which is attached hereto as Appendix C, each of which forms part of the present disclosure.

Provisional Abstract: Embodiments of devices and methods according to the application use an embedded p⁺n⁻n⁺ diode to achieve optical modulation using the free carrier plasma dispersion effect. Embodiments of active optical devices in a deposited microelectronic material can break the dependence on the traditional single layer silicon-on-insulator platform and can lead to monolithic large-scale integration of photonic networks on a microprocessor chip.

Appendix A: Manuscript

Deposited Silicon High-Speed Integrated Electro-Optic Modulator

Abstract: We demonstrate a micrometer-scale electro-optic modulator operating at 2.5 Gbps and 10 dB extinction ratio that is fabricated entirely from deposited silicon. The polycrystalline silicon material exhibits properties that simultaneously enable high quality factor optical resonators and sub-nanosecond electrical carrier injection. We use an embedded p⁺n⁻n⁺ diode to achieve optical modulation using the free carrier plasma dispersion effect. Active optical devices in a deposited microelectronic material can break the dependence on the traditional single layer silicon-on-insulator platform and help lead to monolithic large-scale integration of photonic networks on a microprocessor chip.

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1. Introduction

Photonic networks on a silicon microelectronic chip offer the opportunity to overcome the power and bandwidth limitations in traditional microprocessor interconnects [1, 2]. One critical device for on-chip optical networks is a silicon high-speed waveguide-integrated electro-optic modulator, which converts data from the electrical domain to the optical domain. All previous examples of these modulators (including interferometer [3-7] and microresonator [8-11] geometries) have been fabricated on single-crystalline silicon-on-insulator (SOI) [12]. Reliance on the SOI platform presents two difficult challenges for the integration of optics with microprocessor chips. First, the large-scale integration of hundreds of optical devices would take a prohibitive amount of real estate away from transistors in the same silicon layer, and second, the buried oxide thickness in standard microelectronic SOI is much smaller than the optical wavelength and therefore not appropriate for a waveguide cladding [13, 14]. Here we show the first demonstration of GHz-speed electro-optic modulation in a deposited microelectronic film. The use of deposited material, here polycrystalline silicon (polysilicon), would enable the monolithic integration of optics in a separate layer of a microprocessor chip and provide the flexibility needed for optical system design.

The requirements for both chip real estate and device compatibility indicate that photonic devices and electronic devices should be on separate layers of a microprocessor chip [15]. One option for multilayer integration is to fabricate separate electronic and photonic SOI wafers followed by wafer thinning, bonding, and metallization to connect the layers, however the required processes are not yet cost effective and are therefore not in current production [16]. A simpler, monolithic approach would be to deposit silicon-based layers above the transistor layer and process them into optical devices [17]. Previous active switching or modulating devices in deposited microelectronic films such as silicon nitride or amorphous silicon have relied on the thermo-optic effect [18] which is limited to low speeds in the MHz regime [19]. Liu et al. recently demonstrated a GHz-speed, epitaxially grown GeSi electroabsorption modulator integrated with CMOS circuits [20], however epitaxial growth typically requires a crystalline seed which limits where the material can be grown.

In this work we show integrated electro-optic devices in deposited polysilicon, a standard microelectronic material containing crystalline grains separated by thin amorphous grain boundaries [21]. Previous optical devices in the polysilicon-on-insulator material system included passive waveguides with loss on the order of 10 dB/cm [22-24], optical filters [13, 25], and a recent demonstration of all-optical modulation [26]. Here we demonstrate electrooptic functionality by embedding a p⁺-n⁻-n⁺ diode [27, 28] around a polysilicon ring resonator as shown in FIG. 1. In order to achieve good optical and electrical properties, we use photonic structures with cross sectional dimensions of hundreds of nanometers, on the order of the material grain size [26]. This enables sub-nanosecond carrier injection and optical modulation using the free carrier dispersion effect [29].

FIG. 1. Polysilicon electro-optic modulator device structure. (a) Top view schematic showing the doping regions of the device that form a p⁺-n⁻-n⁺ diode around a ring resonator. (b) Tilted view colorized scanning electron microscope (SEM) image. The polysilicon resonator and 450 nm-wide bus waveguide are buried under 1 μm silicon dioxide. (c) Cross-section schematic of the device (not to scale).

2. Polysilicon Material Properties and Device Fabrication

The polysilicon material system differs from single-crystalline silicon in three critical ways that affect electro-optic modulator design and performance: effective carrier mobility (μ_(eff)), effective free carrier lifetime (τ_(fc)), and optical loss. All three parameters are affected by the grain boundaries that exist throughout the material. For instance, grain boundaries in polysilicon present a potential barrier to the flow of carriers which results in decreased effective carrier mobility μ_(eff) [21, 30]. Mobility in various phases of silicon ranges from the order of 1,000 cm²/V·s (single crystalline silicon) to less than 1 cm²/V·s (amorphous silicon).

Background doping of the device region is required to ensure sufficient charge injection because intrinsic undoped polysilicon is extremely resistive (corresponding to low mobility μ) [21]. An increase in doping above the grain boundary trap density improves the electrical injection [21, 28], but this is a tradeoff with increased optical loss due to free carrier absorption [29]. In doped polysilicon, some percent of dopant atoms segregate to low energy positions at the grain boundaries where they do not contribute carriers. Additionally, the carriers themselves can fill in grain boundary trap states [21] where they will not contribute to free carrier dispersion. To keep the background free carrier losses low, we conservatively choose an average n-type doping level N_(d)≈2·1017 cm⁻³. We estimate that this produces a free carrier concentration n≦10¹⁷ cm⁻³ which keeps excess free carrier loss below 4 dB/cm [29].

Grain boundaries and other intragrain defects in polysilicon induce a fast carrier recombination lifetime, which allows a polysilicon modulator to reach a steady state carrier concentration faster than a comparable crystalline silicon device. This lifetime was measured in previous work to be on the order of τ_(fc)≈100 ps for a grain size of approximately 300 nm in a 450 nm by 250 nm channel waveguide [26]. In addition to decreased τ_(fc) and μ_(eff), optical losses are moderately increased in polysilicon due to scattering and absorption of light at the grain boundaries [22], though resonator quality factors of 20,000 are achievable [25] which is more than sufficient for a modulator device [9].

Fabrication of the devices is performed using standard microelectronic processes. We start with a silicon wafer and grow a 3 μm thermal oxide isolation layer. We then deposit a 270 nm layer of amorphous silicon by low pressure chemical vapor deposition (LPCVD) at 550° C. and crystallize the film into polysilicon by a thermal anneal at a maximum temperature of 1100° C. Background doping of the resonator area is done by opening windows in positive e-beam resist and performing Phosphorus ion implantation with a dose of 4.7×10¹² cm⁻² and energy of 130 keV. We pattern waveguides and resonators using e-beam lithography and XR-1541 resist, and transfer the pattern using chlorine-based inductively coupled plasma reactive ion etching (ICP-RIE), leaving a 40 nm slab of silicon for electrical access. We dope p⁺ and n⁺ contact regions in the slab by BF₂ and Phosphorus ion implantation at 1.2×10¹⁵ cm⁻² dose and clad the structures in 1 μm silicon dioxide by plasma enhanced chemical vapor deposition (PECVD). We then anneal the sample in N₂ for 30 minutes at 600° C., 15 minutes at 900° C., and 15 seconds at 1050° C. for silicon regrowth and dopant activation. (By ending with the high temperature rapid thermal anneal, we maximize the number of dopant ions that are electrically active [21].) Finally we open vias to the contact regions in order to form nickel silicide contacts and aluminum pads using e-beam evaporation and liftoff steps. The device consists of a 10 μm radius polysilicon ring resonator embedded in a 40 nm tall p⁺-n⁻-n⁺ diode and laterally coupled to a polysilicon waveguide. A cross-sectional schematic, top view schematic, and top view microscope image are shown in FIG. 1.

3. Results

We first analyze the electro-optic device with DC measurements. Optical measurements are performed using a tunable infrared laser coupled through a polarization controller to a tapered lens fiber. Light is coupled on and off chip via nanotaper mode converters. Output from the chip is collected by an objective lens, passed through a polarization filter, and focused on a photodetector. FIG. 2( a) shows a measured resonance at λ₀=1550.35 nm with spectral 3 dB width Δλ_(FWHM)=0.45 nm, quality factor Q=λ₀/Δλ_(FWHM)=3,400 and 16 dB extinction ratio.

Other devices from this fabrication run exhibited quality factors exceeding 10,000. We perform a DC electrical measurement on the device to obtain a diode IV curve shown in FIG. 2( b). The device exhibits an on-resistance of approximately 3.5 kΩ, which includes contact resistance at the p⁺ and n⁺ regions and series resistance through the lightly doped waveguide and slab regions.

FIG. 2. DC optical and electrical measurements. (a) Wavelength scan showing through port transmission for quasi-TM polarization with quality factor Q=λ₀/Δλ_(FWHM)=3,400 and 16 dB extinction ratio. (b) Electrical IV curve demonstrating DC diode characteristics.

We demonstrate 2.5 Gbps modulation and measure a 10 dB modulation depth with a NRZ 2⁷-1 PRBS electrical signal applied with a ±4V swing and a 4V DC bias. For AC measurements, output light from the chip is collimated, coupled to a fiber, passed through a fiber pre-amplifier and tunable filter, and recorded by an oscilloscope with a 20 GHz photodetector. The oscilloscope is triggered to the pattern generator which provides the NRZ electrical signal to a high-speed amplifier and bias T circuit. By forward biasing the diode and injecting free carriers into the ring, the resonant wavelength blue shifts and changes the probe wavelength transmission from low to high. FIGS. 3( a) and (b) show the optical transmission and frame-averaged optical eye diagram when the wavelength is tuned to minimize the offstate transmission. The slight overshoot and oscillation of the high transmission of the waveform in FIG. 3 is caused by electrical impedance mismatch, coupled with the fact that the voltage swing here is not sufficient to reach full optical transmission. Comparing the measured 10 dB extinction ratio in FIG. 3( a) to the 16 dB extinction on resonance in FIG. 2( a), we estimate a 6 dB insertion loss and a maximum wavelength shift Δλ≈130 pm. This Δλ corresponds to an effective index shift Δn_(eff)=n_(g) Δλ/λ₀=3.66×10⁻⁴ given a group index n_(g)=4.36 found with a finite difference modesolver program. Based on modesolver simulation, this Δn_(eff) is caused by a silicon refractive index change Δn=3.7×10⁻⁴, which is caused by a carrier injection level ΔN=ΔP=8.4×1016 cm⁻³ [29]. We estimate energy consumption of 950 fJ/bit and power consumption of 2.4 mW based on the voltage swing, bit rate, carrier lifetime, device size, and charge injection levels.

The carrier mobility μ can be estimated from the measured DC on-resistance using the formula [28]:

$\begin{matrix} {R_{on} = {\frac{1}{q\; \mu \; {nw}}\left( {\frac{L_{slab}}{h_{slab}} + \frac{L_{wg}}{h_{wg}}} \right)}} & (1) \end{matrix}$

where q is the electron charge, n is the free carrier concentration (˜10¹⁷ cm⁻³), w is the circumference of the ring (62.8 μm), L_(slab) is the total cross-section length of the slab region between the n⁺ and p⁺ regions (1.55 μm), L_(wg) is the width of the waveguide (0.45 μm), h_(slab) is the height of the polysilicon slab (40 nm), and h_(wg) is the waveguide height (270 nm). By attributing the full 3.5 kΩ to material resistance, we calculate a first-order lower bound for the carrier mobility μ=100 cm²/V·s. This is only one order of magnitude lower than values in crystalline silicon [21], which explains why the electrical performance can approach that seen in crystalline SOI devices.

We model the operation of the device using Silvaco Atlas simulation software and show excellent agreement with experimental results. As a first order model of the effect of grain boundaries on the polysilicon electrical properties, we define silicon bulk material properties within our device, including a free carrier lifetime τ_(fc)=80 ps and an effective carrier mobility μ_(n)=100 cm²/V·s for electrons and μ_(p)=50 cm²/V·s for holes. We use Shockley-Read-Hall and Klaassen models for carrier recombination and mobility, and the surface recombination velocity is taken to be 16,000 cm/s which is consistent with SOI modeling [31]. We apply the same voltage signal as was used in FIG. 3( a) (without ringing) and solve for the transient charge concentrations ΔN(t) and ΔP(t) in the waveguide region. These values are then converted to a wavelength shift Δλ(t) and excess loss Δα(t) which are put into a Lorentzian resonance model to find the optical response. Note that a time domain optical model is not required because the cavity photon lifetime τ_(p)=Qλ/(2πc)=2.7 ps is much less than the charge injection time. The result for optical transmission is shown in FIG. 3( c), which demonstrates excellent agreement in rise time, fall time, and extinction ratio with the experimental results in FIG. 3( a).

FIG. 3. Electro-optic response of the polysilicon modulator. (a) Optical transmission and (b) frame-averaged optical eye diagram for NRZ 2.5 Gbps 2⁷-1 PRBS signal. (c) Simulation of electro-optic response using bulk distributed material parameters τ_(fc)=80 ps, μ_(n)=100 cm²/Vs, and μ_(p)=50 cm²/Vs.

Simulation Parameters:

τ_(fc)=80 ps

μ_(n)=100 cm²/V·s

μ_(p)=50 cm²/V·s

SRV_(n,p)=16,000 cm/s

4. Discussion

The polysilicon device shown here demonstrates speed and energy consumption (2.5 Gbps and 950 fJ/bit) approaching those in state-of-the-art crystalline silicon microresonator devices (˜20 Gbps and ˜100 fJ/bit [9, 10]). The reduced carrier mobility μ in polysilicon necessitates the use of a slightly higher forward bias voltage for the on-state which increases power consumption, however this is partially compensated by the fast carrier recombination [26] which eliminates the need for a reverse bias voltage for the off-state. The optical transmission in FIG. 3 exhibits a 90%-10% fall time of 120 ps with 0V applied for the off-state. The 10%-to-90% rise time in FIG. 3 is 150 ps, indicating a possible bit rate >5 Gbps. With moderately improved Q and electrical characteristics, we expect the insertion loss could be reduced to near 0 dB and the speed increased to tens of Gbps using pre-emphasis techniques [32].

Electrical properties of the device can be improved by two main approaches: optimizing the background doping concentration and decreasing the device size. The background doping strongly influences the electrical mobility and resistance obtained in the film, which in turn strongly affect the speed and power consumption [21, 30]. Optimal conditions may be found at a higher doping concentration N_(d) that further improves the mobility without negatively affecting off-state Q. Energy consumption can be greatly reduced to potentially tens of fJ/bit by decreasing the size of the resonator to smaller microring [33] or 1-D cavity geometries [34, 35], since switching energy scales inversely with resonator size [33].

The primary consideration for photonic integration with the CMOS process flow is the temperature required for device fabrication [17]. The highest temperature in our process is the 1100° C. crystallization anneal which is used to maximize the grain size and minimize the optical loss [22]. Because of the relatively high temperature, these devices would need to be fabricated before any doping or silicidation is performed on the silicon transistor layer. Note however that a high temperature thermal anneal is not fundamentally required for large grain polycrystalline films. Crystallization by nanosecond excimer laser annealing can be used to achieve grain sizes of micrometers without any steady state heating of the substrate. This technique is currently used extensively in the thin film transistor industry to produce polycrystalline films on glass and plastic substrates [36]. With a low-temperature process below 450° C., active polysilicon devices could be integrated with low loss amorphous silicon or silicon nitride waveguides on top of the CMOS metal interconnect layers. This type of post-backend processing would enable optical functionality on a CMOS chip with minimal changes to the microelectronic process flow.

5. Conclusion

For the first time to our knowledge, we have demonstrated GHz-speed electro-optic modulation in a deposited microelectronic material. The polycrystalline silicon exhibits optical and electrical properties which enable modulation of the transmission through a microring resonator on a 150 ps timescale. This work represents a step towards adapting high performance silicon photonic devices for monolithic large-scale integration with standard CMOS microelectronics.

Acknowledgments

This work was supported by Intel Corporation and supervised by M. Reshotko. The authors gratefully acknowledge C. Manolatou for the use of her finite difference code. This work was performed in part at the Cornell NanoScale Facility, a member of the National Nanotechnology Infrastructure Network, which is supported by the National Science Foundation (Grant ECS-0335765).

Appendix B: Examples of Fabrication Methods and Device Embodiments

Exemplary Fabrication Description

Fabrication of the exemplary devices is performed using standard microelectronic processes. We start with a silicon wafer and grow a 3 μm thermal oxide isolation layer. We then deposit a 270 nm layer of amorphous silicon by low pressure chemical vapor deposition (LPCVD) at 550° C. and crystallize the film into polysilicon by a thermal anneal at a maximum temperature of 1100° C. Background doping of the resonator area is done by opening windows in positive e-beam resist and performing Phosphorus ion implantation with a dose of 4.7×10¹² cm⁻² and energy of 130 keV. We pattern waveguides and resonators using e-beam lithography and XR-1541 resist, and transfer the pattern using chlorine-based inductively coupled plasma reactive ion etching (ICP-RIE), leaving a 40 nm slab of silicon for electrical access. We dope p⁺ and n⁺ contact regions in the slab by BF₂ and Phosphorus ion implantation at 1.2×10¹⁵ cm⁻² dose and clad the structures in 1 μm silicon dioxide by plasma enhanced chemical vapor deposition (PECVD). We then anneal the sample in N₂ for 30 minutes at 600° C., 15 minutes at 900° C., and 15 seconds at 1050° C. for silicon regrowth and dopant activation. (By ending with the high temperature rapid thermal anneal, we maximize the number of dopant ions that are electrically active.) Finally we open vias to the contact regions in order to form nickel silicide contacts and aluminum pads using e-beam evaporation and liftoff steps. The device consists of a 10 μm radius polysilicon ring resonator embedded in a 40 nm tall p⁺-n⁻-n⁺ diode and laterally coupled to a polysilicon waveguide. A cross-sectional schematic, top view schematic, and top view microscope image are shown in FIG. 1.

Additional Exemplary Fabrication Description

1) Formation of lower cladding. We use 3 microns, but it can be any value above ˜1 micron. We do it through thermal oxidation (a high temperature process) for demonstration purposes, but it can be done by low temperature plasma enhanced chemical vapor deposition (PECVD) at 400C or below.

2) Amorphous silicon deposition. We use 270 nm. It could be anywhere from 100 nm to 500 nm. We use low pressure chemical vapor deposition (LPCVD) at 550 C. It could be done at lower temperatures by PECVD or e-gun evaporation or sputtering.

3a) The top surface of the amorphous silicon can be encapsulated with another material such as silicon nitride (to prevent oxygen diffusion) or silicon dioxide (to prevent the surface from changing shape).

3b) Crystallize the material into polysilicon. Here we do this with a high temperature anneal at 1100 C. It can also be done by transient laser annealing—this is a very different technique which we now have working after 2 years of work—possibly requiring its own invention disclosure because it is so different.

4) Background doping of the material. This step is necessary to improve the electrical characteristics of the material. We use Phosphorus (n-type) dopant with a concentration around 10¹⁷ cm⁻³. Different dopants could be used, and different concentrations (probably higher) could be used.

The following steps can be similar to electro-optic modulator fabrication in crystalline silicon:

5) Lithography and etching to form the waveguides and resonators. Etch down to leave a 50 nm slab (25-75 nm is probably feasible). We use chlorine-based inductively coupled plasma reactive ion etching (ICP-RIE), but several other etch processes are possible (HBr, SF₆/C₄F₈)

5b) A second lithography and etching step may also be used to remove the slab where you don't need it. This is important for isolating different electrical devices.

6) Heavily dope the p⁺ and n⁺ contact regions of the electrical diode. Dopant concentrations can be anywhere from 10¹⁷ to 10²¹ cm⁻³.

7) Anneal the device in several steps: 600° C. for 30 minutes for silicon regrowth, then 15 minutes at 900° C. and 15 seconds at 1050° C. for dopant activation. The specific times and temperatures could vary widely.

* If doing a low temperature laser annealed device, we will do all of these functions in one low-energy laser annealing step

8) Clad the device in PECVD oxide. We use 1 micron. It could be from, for example, 1-3 microns.

9) Open vias (holes in the oxide) to connect to the device. Deposit nickel (could be different thicknesses or various other metals) and anneal to form a silicide, then deposit aluminum or another metal to form the electrical contact.

It is implied that there are many lithography steps in between all the steps described here. Each lithography step uses a specific type of e-beam resist, thickness, baking time and temperature, and development time. There are many different types of resist chemistries, etc, but the point is just to mask off certain areas of the chip when you do your etching, implantation, etc.

Exemplary physical devices could take many forms, but they all involve some type of optical cavity where light is trapped, with an electrical diode across the device. Different types of exemplary optical cavities include ring resonators, microdisks, and photonic crystals.

Exemplary Embodiments According to the Application

Instead of a being laterally coupled to a polysilicon waveguide, the modulator could be vertically coupled to waveguides that are either above or below the modulator. Possible materials for the bus waveguides include crystalline silicon, amorphous silicon, silicon nitride, and silicon oxynitride. Waveguides below the modulator could be fabricated by lithography and etching and covered in silicon dioxide. A planarization step such as chemical-mechanical polishing (CMP) could be used before deposition of the polysilicon modulator layer on top of the waveguides. Fabrication of the modulator is then carrier out as described previously. Waveguides above the modulator could be made by depositing the waveguide material on top of a silicon dioxide layer covering the modulator. Waveguides could then be patterned by lithography and etching. By working with deposited materials, we open up the possibility for high-density, 3d-integrated optical networks on a silicon chip.

In order to build an optical network on top of a finished CMOS microprocessor chip, the fabrication temperature must be kept below 450° C. This is a desirable case because no changes would need to be made to the CMOS process flow, and optical functionality can be added after the electrical devices are completely finished. The highest temperature in our current process is the 1100° C. crystallization anneal which is used to maximize the grain size and minimize the optical loss. Because of the relatively high temperature, these devices would need to be fabricated before any doping or silicidation is performed on the silicon transistor layer of a CMOS chip. Note however that a high temperature thermal anneal is not fundamentally required for large grain-size polycrystalline films. Crystallization by nanosecond excimer laser annealing can be used to achieve grain sizes of micrometers without any steady state heating of the substrate. This technique is currently used extensively in the thin film transistor industry to produce polycrystalline films on glass and plastic substrates. The top silicon layer is heated by absorption of a UV laser pulse, and the underlying substrate does not undergo steady-state heating. In this way, active silicon electro-optic modulators could be fabricated on any low-temperature substrate, including glass, plastic, or a finished CMOS wafer.

In this section we discussed the possibility of low-temperature formation of the polysilicon by laser annealing. Exemplary steps here include:

1) deposition of thin amorphous silicon (˜150 nm) by e-gun evaporation

2) depositing a silicon dioxide layer (˜50 nm or ˜150 nm) to prevent the surface from getting too rough

3) excimer laser annealing to crystallize the material

4) remove the silicon dioxide by dipping in HF acid

5) chemical-mechanical polishing to reduce the surface roughness, ending at a target thickness of ˜100 nm polysilicon

6) continue with fabrication (etching, doping, metal contact, etc.)

Appendix of Illustrative Embodiments

An illustrative collection of examples of inventive concepts of the present disclosure may thereby be provided as follows:

-   A1. A device comprising:     -   a substrate;     -   a first waveguide comprising polycrystalline silicon positioned         on the substrate;     -   a first optical resonator comprising polycrystalline silicon         positioned on the substrate;     -   a first doped semiconducting region comprising polycrystalline         silicon positioned proximate to the first optical resonator; and     -   a second doped semiconducting region comprising polycrystalline         silicon positioned proximate to the first optical resonator;     -   wherein the first optical resonator is communicatively coupled         to the first waveguide. -   A2. The device of A1, wherein the first doped semiconducting region     is a p-type semiconducting region, and the second doped     semiconducting region is an n-type semiconducting region. -   A3. The device of A2, wherein the p-type semiconducting region     comprises silicon doped with one or more of boron, aluminum, or     gallium. -   A4. The device of A2, wherein the n-type semiconducting region     comprises silicon doped with one or more of phosphorus, arsenic, or     antimony. -   A5. The device of A2, wherein the first optical resonator is doped     with a background doping. -   A6. The device of A5, wherein the background doping has a     concentration of between 10¹¹ and 10¹⁸ charge carriers per square     centimeter, and the p-type semiconducting region and the n-type     semiconducting region are doped with a concentration of between 10¹⁴     and 10²² charge carriers per square centimeter. -   A7. The device of A1, wherein the first waveguide comprises     polycrystalline silicon, the first optical resonator comprises     polycrystalline silicon background doped with a background donor     dopant, the first doped semiconducting region comprises     polycrystalline silicon doped with an acceptor dopant at a higher     density than the background donor dopant in the first optical     resonator, and the second doped semiconducting region comprises     polycrystalline silicon doped with a donor dopant at a higher     density than the background donor dopant in the first optical     resonator. -   A8. The device of A1, further comprising a first conductive contact     connected to the first doped semiconducting region, and a second     conductive contact connected to the second doped semiconducting     region. -   A9. The device of A8, further comprising an insulating layer     disposed over the first optical resonator, the first doped     semiconducting region, the second doped semiconducting region, and     the first waveguide, wherein the first conductive contact and the     second conductive contact extend through the insulating layer. -   A10. The device of A8, further comprising a metal interconnect layer     connected to the first conductive contact and the second conductive     contact. -   A11. The device of A1, wherein the first optical resonator comprises     a ring resonator, the first doped semiconducting region is     positioned interior to the ring resonator, and the second doped     semiconducting region and the first waveguide are positioned     exterior to the ring resonator. -   A12. The device of A1, wherein the first optical resonator comprises     at least one of a ring resonator, a microdisk, or a photonic     crystal. -   A13. The device of A1, wherein the first waveguide has a     cross-sectional dimension within a range of 100 to 2,000 nanometers. -   A14. The device of A1, further comprising additional photonic     structures in a system for multiplexing data in one or more of time,     phase, amplitude, or wavelength. -   A15. The device of A1, further comprising one or more additional     optical resonators that are coupled to the first waveguide and that     are comprised, with the first optical resonator, in an array of     optical resonators. -   A16. The device of A15, wherein the optical resonators in the array     have a plurality of different radii, thereby enabling multiplexing     data in multiple wavelengths in the first waveguide. -   A17. The device of A15, wherein the array comprises tuning     mechanisms associated with a plurality of the optical resonators     that enable the optical resonators to be in communication with the     first waveguide at different times, thereby enabling time     multiplexing in the first waveguide. -   A18. The device of A1, wherein the substrate is formed from at least     one of silicon, germanium, or a compound semiconductor. -   A19. The device of A1, wherein the first optical resonator is     positioned vertically proximate to the first waveguide on different     deposited layers of the substrate. -   A20. The device of A1, further comprising a tuning mechanism based     on at least one of an electrical, thermal, magnetic, photoelectric     or microfluidic effect. -   A21. The device of A1, wherein the first waveguide is formed at     least mostly from at least one of polycrystalline silicon, silicon     nitride, or hydrogenated amorphous silicon. -   A22. The device of A1, further comprising a second waveguide     positioned on the substrate, wherein the first optical resonator is     also communicatively coupled to the second waveguide, such that the     device may function as a switch between the first waveguide and the     second waveguide. -   A23. A method comprising:     -   providing an insulating base layer;     -   forming an amorphous semiconductor layer on the base layer;     -   modifying at least a portion of the amorphous semiconductor         layer into a polycrystalline semiconductor layer;     -   background doping a target area of the polycrystalline         semiconductor layer;     -   forming a waveguide and a resonator in the polycrystalline         semiconductor layer, comprising at least one step of lithography         and/or etching, wherein the resonator is formed in the         background doped target area;     -   forming a p-type region in the polycrystalline semiconductor         layer proximate to the resonator, comprising at least one step         of applying a p-type dopant; and     -   forming an n-type region in the polycrystalline semiconductor         layer proximate to the resonator, comprising at least one step         of applying an n-type dopant. -   A24. The method of A23, wherein forming the amorphous semiconductor     layer on the base layer comprises depositing amorphous silicon using     low pressure chemical vapor deposition. -   A25. The method of A23, wherein modifying at least a portion of the     amorphous semiconductor layer into a polycrystalline semiconductor     layer comprises annealing the amorphous semiconductor layer, wherein     the annealing comprises applying a laser with a wavelength of less     than or equal to 400 nanometers and a pulse period of less than or     equal to 200 nanoseconds to the amorphous semiconductor layer. -   A26. The method of A23, further comprising annealing the     polycrystalline semiconductor layer after forming the waveguide, the     resonator, the p-type region, and the n-type region in the     polycrystalline semiconductor layer, wherein annealing the     polycrystalline semiconductor layer comprises baking the     polycrystalline semiconductor layer for two or more periods at     temperatures within a range of 600 to 1,050 degrees Celsius. -   A27. The method of A23, wherein background doping the target area of     the polycrystalline semiconductor layer comprises using phosphorus     ion implantation; applying the p-type dopant for forming the p-type     region comprises using boron difluoride implantation; and applying     the n-type dopant for forming the n-type region comprises using     phosphorus ion implantation. -   A28. The method of A23, wherein the amorphous semiconductor layer is     formed with a thickness within a range of 100 to 500 nanometers, and     wherein forming the resonator comprises etching the polycrystalline     semiconductor layer to form slabs with a thickness within a range of     25 to 75 nanometers defining an exterior of the resonator. -   A29. The method of A23, further comprising: providing an insulating     cladding on the polycrystalline semiconductor layer; forming vias in     contact with the p-type region and the n-type region through the     insulating cladding; and forming conductive contacts on surfaces of     the vias.

While various embodiments have been particularly shown and described, it will be understood by those skilled in the art that various combinations of the disclosed elements or changes in detail may be made without departing from the spirit and scope of the claims. Further, while in numerous cases herein wherein systems and apparatuses and methods are described as having a certain number of elements it will be understood that such systems, apparatuses and methods can be practiced with fewer than or more than the mentioned certain number of elements. Also, while a number of particular embodiments have been described, it will be understood that features and aspects that have been described with reference to each particular embodiment can be used with each remaining particularly described embodiment. Many variations may also be made within the realm of different embodiments, limited only by the scope of the claims as recited below. 

1. A device comprising: a substrate; a first waveguide comprising polycrystalline silicon positioned on the substrate; a first optical resonator comprising polycrystalline silicon positioned on the substrate; a first doped semiconducting region comprising polycrystalline silicon positioned proximate to the first optical resonator; and a second doped semiconducting region comprising polycrystalline silicon positioned proximate to the first optical resonator; wherein the first optical resonator is communicatively coupled to the first waveguide.
 2. The device of claim 1, wherein the first doped semiconducting region is a p-type semiconducting region, and the second doped semiconducting region is an n-type semiconducting region.
 3. The device of claim 2, wherein the p-type semiconducting region comprises silicon doped with one or more of boron, aluminum, or gallium.
 4. The device of claim 2, wherein the n-type semiconducting region comprises silicon doped with one or more of phosphorus, arsenic, or antimony.
 5. The device of claim 2, wherein the first optical resonator is doped with a background doping.
 6. The device of claim 5, wherein the background doping has a concentration of between 10¹¹ and 10¹⁸ charge carriers per square centimeter, and the p-type semiconducting region and the n-type semiconducting region are doped with a concentration of between 10¹⁴ and 10²² charge carriers per square centimeter.
 7. The device of claim 1, wherein the first optical resonator comprises polycrystalline silicon background doped with a background donor dopant, the first doped semiconducting region comprises polycrystalline silicon doped with an acceptor dopant at a higher density than the background donor dopant in the first optical resonator, and the second doped semiconducting region comprises polycrystalline silicon doped with a donor dopant at a higher density than the background donor dopant in the first optical resonator.
 8. The device of claim 1, further comprising a first conductive contact connected to the first doped semiconducting region, and a second conductive contact connected to the second doped semiconducting region.
 9. The device of claim 8, further comprising an insulating layer disposed over the first optical resonator, the first doped semiconducting region, the second doped semiconducting region, and the first waveguide, wherein the first conductive contact and the second conductive contact extend through the insulating layer.
 10. The device of claim 8, further comprising a metal interconnect layer connected to the first conductive contact and the second conductive contact.
 11. The device of claim 1, wherein the first optical resonator comprises a ring resonator, the first doped semiconducting region is positioned interior to the ring resonator, and the second doped semiconducting region and the first waveguide are positioned exterior to the ring resonator.
 12. The device of claim 1, wherein the first optical resonator comprises at least one of a ring resonator, a microdisk, or a photonic crystal.
 13. The device of claim 1, wherein the first waveguide has a cross-sectional dimension within a range of 100 to 2,000 nanometers.
 14. The device of claim 1, further comprising additional photonic structures in a system for multiplexing data in one or more of time, phase, amplitude, or wavelength.
 15. The device of claim 1, further comprising one or more additional optical resonators that are coupled to the first waveguide and that are comprised, with the first optical resonator, in an array of optical resonators.
 16. The device of claim 15, wherein the optical resonators in the array have a plurality of different radii, thereby enabling multiplexing data in multiple wavelengths in the first waveguide.
 17. The device of claim 15, wherein the array comprises tuning mechanisms associated with a plurality of the optical resonators that enable the optical resonators to be in communication with the first waveguide at different times, thereby enabling time multiplexing in the first waveguide.
 18. The device of claim 1, wherein the substrate is formed from at least one of silicon, germanium, or a compound semiconductor.
 19. The device of claim 1, wherein the first optical resonator is positioned vertically proximate to the first waveguide on different deposited layers of the substrate.
 20. The device of claim 1, further comprising a tuning mechanism based on at least one of an electrical, thermal, magnetic, photoelectric or microfluidic effect.
 21. The device of claim 1, wherein the first waveguide is formed at least mostly from at least one of polycrystalline silicon, silicon nitride, or hydrogenated amorphous silicon.
 22. The device of claim 1, further comprising a second waveguide positioned on the substrate, wherein the first optical resonator is also communicatively coupled to the second waveguide, such that the device may function as a switch between the first waveguide and the second waveguide.
 23. A method comprising: providing an insulating base layer; forming an amorphous semiconductor layer on the base layer; modifying at least a portion of the amorphous semiconductor layer into a polycrystalline semiconductor layer; background doping a target area of the polycrystalline semiconductor layer; forming a waveguide and a resonator in the polycrystalline semiconductor layer, comprising at least one step of lithography and/or etching, wherein the resonator is formed in the background doped target area; forming a p-type region in the polycrystalline semiconductor layer proximate to the resonator, comprising at least one step of applying a p-type dopant; and forming an n-type region in the polycrystalline semiconductor layer proximate to the resonator, comprising at least one step of applying an n-type dopant.
 24. The method of claim 23, wherein forming the amorphous semiconductor layer on the base layer comprises depositing amorphous silicon using low pressure chemical vapor deposition.
 25. The method of claim 23, wherein modifying at least a portion of the amorphous semiconductor layer into a polycrystalline semiconductor layer comprises annealing the amorphous semiconductor layer, wherein the annealing comprises applying a laser with a wavelength of less than or equal to 400 nanometers and a pulse period of less than or equal to 200 nanoseconds to the amorphous semiconductor layer.
 26. The method of claim 23, further comprising annealing the polycrystalline semiconductor layer after forming the waveguide, the resonator, the p-type region, and the n-type region in the polycrystalline semiconductor layer, wherein annealing the polycrystalline semiconductor layer comprises baking the polycrystalline semiconductor layer for two or more periods at temperatures within a range of 600 to 1,050 degrees Celsius.
 27. The method of claim 23, wherein background doping the target area of the polycrystalline semiconductor layer comprises using phosphorus ion implantation; applying the p-type dopant for forming the p-type region comprises using boron difluoride implantation; and applying the n-type dopant for forming the n-type region comprises using phosphorus ion implantation.
 28. The method of claim 23, wherein the amorphous semiconductor layer is formed with a thickness within a range of 100 to 500 nanometers, and wherein forming the resonator comprises etching the polycrystalline semiconductor layer to form slabs with a thickness within a range of 25 to 75 nanometers defining an exterior of the resonator.
 29. The method of claim 23, further comprising: providing an insulating cladding on the polycrystalline semiconductor layer; forming vias in contact with the p-type region and the n-type region through the insulating cladding; and forming conductive contacts on surfaces of the vias. 